USB-RAM (tm)

General Purpose USB Client Interface device

Advance Information

Update 31 Mar 2002 - The USB-RAM supports USB1.1 Full Speed mode and includes the USB drivers (Low Speed bus is not supported). The device operates at 3.3v and is 5V tolerant on the data input signals. The 48 Mhz required by USB is internally generated from a 12 MHz clock. Prototype USB-RAM will be available in 44-pin PLCC with 4K bytes dual-port-RAM. Available 2Q 2002. A prototyping board with an 8051 socket will also be available. Please send email to be kept advised of latebreaking news.

The USB-RAM is a dedicated controller designed for the USB client (peripheral) interface. It is not a microprocessor or microprocessor-like device that must be programmed by the user. This fact simplifies the device and its use, making the USB-RAM the ideal USB part for general-purpose USB interfaces.

The USB-RAM has a USB client interface on one side and RAM plus interrupt on the other side. Both the USB and the client processor share an internal 2K-byte dual port RAM. When the client CPU wants to send a packet, it simply writes the packet into RAM, then writes a command to the USB-RAM. The packet is sent automatically. When a packet is received from the host, the packet is stored in RAM and an interrupt is generated to the client processor.

The USB-RAM supports 16 endpoints (channels), each of which can be any type: control, interrupt, isochronous, or bulk. The endpoint type, status, and memory buffer pointers and lengths are stored in 16 endpoint registers, which are mapped into the dual port RAM. The client processor sets up the registers for outgoing packets and reads the registers to find where received packets are stored.

USB timing and protocols are managed by the device on a per-endpoint basis. Desired endpoint configurations are specified by the client to the host during the initial configuration process. Thereafter, each endpoint has the assigned type, and the USB-RAM manages the endpoint according to the proper protocol for this type, including framing and error handling.

When the client processor wishes to SEND A PACKET, it copies the packet into RAM, then sets up the packet pointer and length counter in the relevant endpoint register and issues a "send" command to USB-RAM.

When a PACKET IS RECEIVED from the host, the USB-RAM copies the received packet into the RAM at the location specified by the relevant endpoint register, records the length of the packet, and interrupts the client processor, with an endpoint-specific interrupt code. The client processor reads this code, which identifies the endpoint, then reads the endpoint register to find the pointer to the packet and the length of the packet. The client sets a "ready" bit in the endpoint register to tell the USB-RAM that it has handled the last received packet, and is ready for the next. After a packet has been received from the host, the USB-RAM will "auto-NAK" until the client sets the "ready" bit, thereby preventing packet over-runs.

A USB-RAM Prototyping Board will initially be available for implementation of an 8051-based client application. The board supports a 40-pin DIP 8051 with a wirewrap area, LEDs on port 1, crystal and reset, a Max233 serial driver on Rx/Tx, and post access to all signals. A Motorola board will follow, but until then, the appropriate signals for a Motorola or alternate controller are available at the wirewrap area of the 8051 board.

Protected by US Patent #6,219,736. Other patents pending. USB-RAM is a trademark of Cybernetic Micro Systems.