P-51 Documentation
		    ERRATA/ADDENDA
		Cybernetic Micro Systems
		  22 September 2000
		  29 January 2001
		  21 November 2002

===============================================================

P51 User manual (5/30/00) errata:
---------------------------------------------

Page 4:

P-51 Pin List

RFRSH (pin 11 - input) description should be reversed to say:

ISA Refresh, low during a refresh cycle, 
high during a normal cycle.

When connected to the ISA bus, the ISA Refresh signal drives 
the P-51 RFRSH input directly.  The pin has an internal pullup 
so if it is connected to a micro-controller, the P-51 refresh 
signal should be pulled high or left open.

---------------------------------------------

Page 22:

	was: 

9. ...(Base + 0x3E2F => P-51 Code Address 0x2E2F)

	should be:
 
9. ...(Base + 0x1E2F => P-51 Code Address 0x0E2F)

---------------------------------------------

Page 22:

	was:

11. After the Wait flag is cleared, the P-51 will 
execute the code from address 0x2E2F ...

	should be:

11. After the Wait flag is cleared, the P-51 will 
execute the code from address 0x0E2F ...

---------------------------------------------

Page 33, Last item in "Special Memory Function Locations" Table:

	was:

BASE + 0x3E2F 
  Breakpoint Subroutine
    Code 0x2E2F
      Start of P51 Subroutine executed after a breakpoint

	should be:

BASE + 0x1E2F 
  Breakpoint Subroutine
    Code 0x0E2F
      Start of P51 Subroutine executed after a breakpoint


===============================================================

Addenda:

Movx Latch

  The "movx" instructions in the P51 are identical to the "movx" 
  instructions in the 8051, with respect to the read and write signals, 
  P3.6 and P3.7, and to address and data on P2 and P0. This is true 
  whether the target of the "movx" is internal or external; that is, 
  whether the P51 is accessing the internal dual port RAM or an external 
  RAM/IO-device.

  A consequence of this is that systems that use only internal dual port 
  RAM will still see P2:P0 changes (and P3.6,P3.7) when "movx" occurs. 
  If these ports are intended to drive external devices, then latches 
  may be required on P2 and P0 to shield the external devices from "movx" 
  induced changes.

  Similarly, if external RAM-I/O is used, the external RAM must be 
  disabled during internal "movx" operations. This will normally be 
  done using P1.6 as chip select.


2E2F breakpoint address:

  When a breakpoint occurs, the P51 indicates that the next instruction 
  will be at 2E2F. Since the current version P51 has only 8K of RAM, 2E2F 
  is outside of the address space, and execution actually occurs at 0E2F, 
  ignoring the highest bit. Note that if you actually use 2E2F the P51 will 
  work, ignoring the msbit and using 0E2Fh.